library verilog;
use verilog.vl_types.all;
entity alu_hier is
    port(
        a               : in     vl_logic_vector(15 downto 0);
        b               : in     vl_logic_vector(15 downto 0);
        op              : in     vl_logic_vector(3 downto 0);
        \Out\           : out    vl_logic_vector(15 downto 0);
        ofl             : out    vl_logic;
        z               : out    vl_logic
    );
end alu_hier;
